Method and resulting structure for manufacturing semiconductor substrates

ABSTRACT

A method of manufacturing bonded substrates. The method includes providing a metallic substrate. The metal substrate has a predetermined thickness. The method also includes bonding a first thickness of compound semiconductor material overlying the metallic substrate and reducing a thickness of the first thickness of compound semiconductor material to a second thickness. The method includes forming one or more via structures through a portion of the second thickness of compound semiconductor material to a portion of the underlying metal substrate, whereupon the via structure electrically connects to the metal substrate.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a divisional of U.S. Ser. No. 10/634,512 (AttorneyDocket No. 022331-000220) filed Aug. 4, 2003, which is a continuation inpart of U.S. Ser. No. 10/389,278 (Attorney Docket No. 21498-000210US)filed Mar. 13, 2003, which claims priority to Australian ProvisionalPatent Application No. PS1122 filed Mar. 14, 2002, commonly assigned,and hereby incorporated by references for all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH OR DEVELOPMENT BACKGROUND OF THE INVENTION

The present invention relates generally to manufacturing substrates.More particularly, the invention provides a method and device forimproved semiconductor substrates to form advanced semiconductordevices. Merely by way of example, the invention has been applied to ametallic substrate that includes a plurality of panels and/or tiles,which are bonded on the substrate, for the manufacture of the advancedsemiconductor devices. But it would be recognized that the invention hasa much broader range of applicability.

As technology progresses, semiconductor manufacturers have continuallystrived to use ever larger wafers to obtain economies of scale, andconsequently lower the cost of individual semiconductor devices.Commonly, silicon crystal boules can be readily grown large enough toslice into 12 inch diameter wafers. The 12 inch wafers have beenproduced for single crystal silicon materials for a variety ofapplications. Although the single crystal silicon has many benefits,there are still numerous disadvantages.

Many conventional industries have been increasingly reliant on compoundsemiconductor devices fabricated from compound semiconductors such asgallium arsenide, indium phosphide, and gallium nitride. Unfortunately,integrated circuits made from these semiconducting compounds are stillrelatively expensive compared to circuits made from siliconsemiconductors. This cost difference is largely attributable to therespective material costs, and wafer processing costs. Other limitationsalso exist with compound semiconductor materials.

Compound semiconductor wafers are more prone to damage. For example,they are more brittle than conventional single crystal silicon wafers.Growing large crystal boules of compound semiconductor material isextremely difficult compared with growing large single crystal siliconboules. The maximum diameters for commercially-produced compoundsemiconductor wafers of gallium arsenide, indium phosphide and galliumnitride are respectively six inches, four inches and two inches inconventional commercial applications.

Larger compound semiconductor wafers would be desirable. Unfortunately,larger diameter wafers are difficult to make efficiently. Even if largerboules of compound semiconductor material could be produced, handlingthe resulting large-diameter compound semiconductor wafers wouldgenerally be problematic. Compound semiconductor wafers of the desiredthickness and diameter would be extremely fragile and prone to breakage.Here, the larger wafers would generally break due to the brittle natureof these semiconductor compounds. Accordingly, certain techniques havebeen proposed to manufacture larger compound semiconductor wafers usingan epitaxial grown layer.

As merely an example, a conventional process for fabricating compoundsemiconductor chips could be outlined in steps (i) to (vii) listedbelow.

-   -   (i) Grow epitaxial device layers on mono-crystalline substrate.    -   (ii) Pattern these epitaxial layers and other deposited        dielectric and metallic layers using photolithographic        techniques.    -   (iii) Bond wafers face-down to a temporary supporting substrate        after front-side process is complete.    -   (iv) Thin wafers by mechanical grinding or lapping back-side.    -   (v) Create “via holes” in the substrate, which provide a means        for connecting the back-side ground to appropriate front-side        ground connections.    -   (vi) Deposit a metal film on the wafer's back-side to provide a        ground plane, and coat the walls of the via holes, thereby        making contact with the front-side ground connections.    -   (vii) Dice wafer into individual chips.

In the above conventional process, wafers are typically 625 μm inthickness during steps (i), (ii) and (iii), and have sufficientmechanical strength to avoid breakage with careful handling. Wafers aretypically thinned to around 50 to 100 μm in thickness in step (iv).Thinning wafers has numerous advantages, which relate to:

-   -   (i) reducing the depth (and also the size) of via holes, as well        as parasitic inductance associated with the via holes;    -   (ii) conducting heat away from front-side devices towards the        back-side, which is normally attached to a heat sink; and    -   (iii) preventing electromagnetic resonance in the substrate at        high frequencies.

Handling thinned compound semiconductor wafers is often difficult, andcompound semiconductor wafers are commonly broken from step (iv)onwards. Breakage is costly, since most of the processing (steps (i) to(iii)) is already complete. The fragility of compound semiconductormaterials also causes breakages of resulting chip devices, and restrictsthe larger size of practical chip designs that use compoundsemiconductor materials. Here, larger sized compound semiconductormaterials are not practical to make efficiently.

In conventional compound semiconductor wafer processing, via holes arealso required to connect certain grounded circuit elements on the frontside of the wafer to the ground plane on the back side. Typically thesevia holes are etched from the back side of the wafer towards the frontside elements. Certain limitations exist with processing of via holesfor compound semiconductor wafers. Difficulties often arise because of aneed to align features on one side of the wafer with correspondingfeatures on the other side of the wafer. Alignment tolerances of thesevia hole features are therefore poor. Additionally, there is often arestriction on the number and shape of via holes because they reduce themechanical strength of the wafer. These and other limitations have beendescribed throughout the present specification and more particularlybelow.

In view of the above, a need exists for improved techniques forproducing and handling semiconductor wafers. In particular, a needexists for techniques suitable for assisting practical andcost-effective production of compound semiconductor devices.

BRIEF SUMMARY OF THE INVENTION

According to the present invention, techniques for manufacturingsubstrates are provided. More particularly, the invention provides amethod and device for improved semiconductor substrates to form advancedsemiconductor devices. Merely by way of example, the invention has beenapplied to a metallic substrate that includes a plurality of panelsand/or tiles, which are bonded on the substrate, for the manufacture ofthe advanced semiconductor devices. But, it would be recognized that theinvention has a much broader range of applicability.

In a specific embodiment, the invention provides a method ofmanufacturing bonded substrates. The method includes providing ametallic substrate. The metal substrate has a predetermined thickness.The method also includes bonding a first thickness of compoundsemiconductor material overlying the metallic substrate and reducing athickness of the first thickness of compound semiconductor material to asecond thickness. The method includes forming one or more via structuresthrough a portion of the second thickness of compound semiconductormaterial to a portion of the underlying metal substrate, whereupon thevia structure electrically connects to the metal substrate.

In an alternative specific embodiment, the invention provides a methodfor manufacturing composite substrates for semiconductor devices. Themethod includes providing a metal substrate, which has a first diameterand a bonding surface. The method includes bonding a plurality of tilesoverlying the bonding surface. Each of the tiles is coupled to a portionof the bonding surface. Each of the tiles has a shape and size to beable to form an array configuration. The method also includes elevatinga temperature of the plurality of tiles and metal substrate and forminga eutectic bond between each of plurality of tiles and portion of thebonding surface. The elevating of the temperature is provided while eachof the tiles is substantially stationary relative to the metalsubstrate. The method forms a plurality of active devices on each of theplurality of tiles and forms a plurality of openings through each oftiles. Each of the openings traverses through a portion of one of thetiles through a portion of the eutectic bond to a portion of the metalsubstrate to form a via structure. Additionally, the method includesforming an interconnect layer to connect the portion of the one of theactive devices through the portion of the tile through the eutectic bondto the portion of the metal substrate. The interconnect layer thatconnects the portion of one of the active devices through the portion ofone of the tiles through the portion of the eutectic bond to the portionof the metal substrate.

In still an alternative specific embodiment, the invention includes amethod of manufacturing bonded substrates. The method includes providinga metallic substrate, which has a predetermined thickness. The methodalso includes bonding a first thickness of compound semiconductormaterial overlying the metallic substrate and reducing a thickness ofthe first thickness of compound semiconductor material to a secondthickness. The method also forms a trench region surrounding a portionof the second thickness of the compound semiconductor material.Additionally, the method forms a conductive material within the trenchregion to isolate the portion of the second thickness of the compoundsemiconductor using the conductive material in the trench region and aportion of the underlying metallic substrate.

In yet an alternative embodiment, the invention provides a substratestructure for high frequency devices. The substrate structure includes ametallic substrate, which is used as a ground plane for a high frequencyamplifying device operable at a frequency greater than 10 G Hz. Acompound semiconductor material is bonded to the metallic substrate. Oneor more via structures for ground connections is formed within portionsof the compound semiconductor material. The one or more via structuresis electrically connected to the metallic substrate. The one or more viastructures is configured to provide a desired reactance to provide auniversal ground reference. The universal ground reference is within apredetermined amount.

Still further, the invention provides an integrated circuit devicestructure. The integrated circuit device structure includes a metallicsubstrate, which has a predetermined thickness and a predeterminedthermal conductivity. A thickness of compound semiconductor material isbonded to a surface overlying the metallic substrate. A trench region isdisposed within a portion of the thickness of the compound semiconductormaterial and extending to a portion of the metallic substrate. A thermalconductive material is formed within the trench region and thermallycoupled to the portion of the metallic substrate. The thermal conductivematerial is coupled to the portion of the thickness of the compoundsemiconductor to redistribute thermal energy among the portion of thecompound semiconductor, the thermal conductive material, and themetallic substrate.

Various advantages can be achieved through use of a semiconductor tilebonded to a metallic substrate. The semiconductor wafer composite isless fragile than the semiconductor tile, and can thus be handled inlarger areas. As a result, cost savings can be achieved through largervolume fabrication. In particular, compound semiconductor wafers thathave been hitherto produced from smaller diameter wafers can beprocessed in any effective size through the use of multiplesemiconductor tiles. Consequently, existing fabrication equipment fortreating 12 inch diameter silicon wafers can be used to fabricatecompound semiconductor devices using the described semiconductor wafercomposite. Other benefits can also be achieved in one or moreembodiments, as follows:

-   -   1) There can be more via holes without reducing structural        strength of wafer;    -   2) The via holes can be any shape including trenches without        reducing structural strength;    -   3) The trenches can be arranged to almost entirely enclose a        particular circuit or circuit element thereby providing        electromagnetic shielding, thermal isolation or heat spreading;    -   4) The trenches can be arranged with underlying metal substrate        and overarching metallic “air bridges” to form sidewalls, bottom        and top respectively of electromagnetically screened on-chip        “metal boxes” which can be used to isolate circuit elements from        sources of interference;    -   5) The via holes and trenches are formed using a front side        process which is easily aligned to other front side features.        Depending upon the embodiment, one or more of these benefits may        be achieved. These and other benefits are described throughout        the present specification and more particularly below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic representation of a view, from above,of a semiconductor wafer composite comprising a circular metallicsubstrate on which four square semiconductor tiles are bonded accordingto an embodiment of the present invention.

FIG. 2 is a simplified cross-sectional view corresponding with FIG. 1.

FIG. 3 is a simplified flowchart of a method involved in fabricatingsemiconductor chips from the semiconductor wafer composite of FIGS. 1and 2 according to an embodiment of the present invention;

FIGS. 4-7 illustrate a simplified method of forming a via structureaccording to an embodiment of the present invention;

FIG. 8 is a simplified plot of a frequency characteristic of a viastructure according to an embodiment of the present invention; and

FIGS. 9-15 illustrate a simplified method of forming a semiconductordevice according to an alternative embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

According to the present invention, techniques for manufacturingsubstrates are provided. More particularly, the invention provides amethod and device for improved semiconductor substrates to form advancedsemiconductor devices. Merely by way of example, the invention has beenapplied to a metallic substrate that includes a plurality of panelsand/or tiles, which are bonded on the substrate, for the manufacture ofthe advanced semiconductor devices. But it would be recognized that theinvention has a much broader range of applicability.

A semiconductor wafer composite is described herein. The composite iswell suited to fabrication of compound semiconductor devices. Further,the composite has particular application in the context of large scaleproduction of such devices. The semiconductor wafer composite from whichthe individual semiconductor devices are fabricated is first described,followed by a procedure for high volume production of semiconductordevices using the described semiconductor wafer composite.

FIGS. 1 and 2 schematically represent a simplified semiconductor wafercomposite, using top and side views respectively according to anembodiment of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims herein. One ofordinary skill in the art would recognize many variations,modifications, and alternatives. The semiconductor wafer compositeeffectively replaces existing semiconductor wafers from whichsemiconductor chip devices are fabricated.

The described semiconductor wafer composite represented in FIGS. 1 and 2comprises a metallic substrate 210 upon which is bonded a number ofsemiconductor tiles 220.

FIG. 1 represents the metallic substrate 210 as circular in shape, andrepresents four abutting rectangular semiconductor tiles 220. The fourrectangular shapes shown in dotted outline represent further rectangularsemiconductor tiles 220 that may be bonded to the metallic substrate 210near the periphery of the metallic substrate 210, to more efficientlyuse the surface of the metallic substrate 210. The substrate ispreferably made from materials which have good electrical and thermalconductivity and whose coefficient of thermal expansion matches that ofthe semiconductor tiles. For example, CuMo, AlSi and Mo are suitablematerials. Preferably, the substrate is highly conductive withresistivity in the range 1 to 10 micro ohm centimeters (1-10×10⁻⁶ohm-cm) according to a specific embodiment. Alternatively, the materialcan be semiconductor according to other embodiments. The tiles 220 areclosely placed together, through perhaps not directly abutting. A slightspacing between wafer tiles 220 eases tile dimension accuracyrequirements and allows for slight thermal expansion gaps, if desirable.Indicative gap dimensions may be, for example, less than 5 μm.Preferably, each of the tiles should have a slight gap to separate themfrom each other to account for any differences in tolerances.Alternatively, the tiles are abutting each other to prevent or reduceimpurities (e.g., photoresist) from entering regions between the tilesaccording to other embodiments.

FIG. 2 is a side view that corresponds with FIG. 1. The peripheralsemiconductor tiles 220 depicted in dotted outline in FIG. 1 are notrepresented in FIG. 2. The metallic substrate 210 comprises a metallicbase layer 240, upon which is formed a metallic bonding layer 250. Themetallic base layer 240 may be formed of a suitable metal or alloys thatmatches the coefficient of thermal expansion (CTE) of the compoundsemiconductor material. For a gallium arsenide (GaAs) compoundsemiconductor tile 220, a suitable choice of metallic substrate 210 iscopper molybdenum (CuMo). The metallic bonding layer 250 is desirablyformed of tin (Sn) or indium (In) and gold (Au), or other suitablemetals having a relatively low melting point, and which form a eutecticalloy upon heating. In preferred embodiments, the eutectic alloy isprovided purely from compression and free from relative lateral movementbetween the tile and substrate.

The semiconductor tiles 220 comprise a working layer 260 of compoundsemiconductor material (such as gallium arsenide (GaAs)), and acomplementary bonding layer 270 preferably formed of a material thatassists the semiconductor tile 220 to adhere to the metallic substrate210. A suitable material is a combination of titanium (Ti) and gold(Au).

Surrounding the metallic base layer 240 and metallic bonding layer 250is a thin metallic coating layer 290, formed of a noble metal. Gold (Au)or platinum (Pt) is preferably used. The coating layer 290 seals themetallic substrate 210 from damage during subsequent fabrication ofsemiconductor devices from the semiconductor wafer composite. Thecoating layer 290 can be applied by evaporation/deposition techniques,or by electroplating, for example.

While components of the semiconductor wafer composite are describedabove with reference to FIGS. 1 and 2, various other associated featuresand advantages of the semiconductor wafer composite are described belowwith reference to a process for manufacturing the semiconductor wafercomposite. This manufacturing process is described herein with referenceto steps 310 to 330 of FIG. 3. Remaining steps 340 to 370 of FIG. 3describe subsequent steps in fabricating semiconductor devices from thesemiconductor wafer composite.

In a specific embodiment, each of the tiles has a specific size andshape. The metal substrate also has a desired shape and size. That is,the metal substrate has a diameter “dm”, which is chosen according tothe capabilities of the intended wafer processing equipment. Thisdimension is preferably selected from a set of industry diameters, e.g.,2 inch, 3 inch, 4 inch, 5 inch, 6 inch, 8 inch, 12 inch. The substrateis shaped to provide a “flat” on one part of the circumference that actsas an alignment reference, which is similar to conventional wafers.

Further, the substrate may be patterned to provide apertures which aidpackaging operations or which facilitate the coupling of signals offchip. For example, the apertures may be used to form slots which radiatehigh frequency signals off chip.

The tiles would be cut from circular compound semiconductor wafers ofradius “ds” where an integral number of wafer diameters “ds” equate tothe metal substrate diameter “dm” ie dm=n×ds where n is the smallestpossible integer. This relationship ensures the least number of tilesand minimum wastage of expensive compound semiconductor material incutting tiles to the appropriate shape. For example, four square tileswith 3 inch diagonal dimensions could be cut from 3 inch semiconductorwafers to cover a six inch metallic substrate in a 2×2 tile array. Ifonly 2 inch diameter semiconductor wafers were available, nine squaretiles with 2 inch diagonals could be prepared to cover a six inchsubstrate in a 3×3 array. Of course, there would be variousmodifications, alternatives, and variations.

Although the semiconductor wafer described above is illustrated using aspecific embodiment, there can be many variations, alternatives, andmodifications. For example, the metal substrate can be made of an alloyor other material, as well as other multilayered materials and the like,which have desirable electrical and thermal characteristics. The metalsubstrate can also be multi-layered, depending upon the application.Additionally, one or more of the tiles can be made of a differentmaterial on the substrate. These and other variations can be foundthroughout the present specification and more particularly below.

In a specific embodiment, a method for fabricating compoundsemiconductor devices involves, in overview, the steps listed below inTable 1. FIG. 3 flowcharts these steps, which are described in furtherdetail below. TABLE 1 Step 310 Multiple semiconductor wafers are thinned220. Step 320 The wafers 220 are cut to form semiconductor tiles. Step330 The semiconductor tiles 220 are bonded to the metallic substrate210. Step 340 Standard front-side processing techniques are used tofabricate devices. Step 350 Via holes are opened from the front-side tothe metallic substrate 210. Step 360 Via holes are metalized to makeground connections to the metallic substrate 210. Step 370 The metallicsubstrate 210 is cut to separate individual chips.

As shown above, the above steps are merely illustrative. Depending uponthe embodiment, certain steps can be further separated or even combinedwith other steps. Additional steps can be added depending upon theembodiment. Other steps can replace certain steps above. Accordingly,there can be many variations, modifications, and alternatives. Furtherdetails of each the steps can be found throughout the presentspecification and more particularly below.

Thinning Semiconductor Tiles—Step 310

Individual wafer tiles 220 are thinned according to existing processingtechniques. If the wafers break at this point, the associated cost isrelatively low since the front side of the semiconductor tile 220 hasnot been processed. According to a specific embodiment, tiles arethinned using a lapping/grinding and/or polishing operation. The tilescan be thinned to a thickness of about 50 to 100 microns according tocertain embodiments. According to a specific embodiment, tiles arethinned using a lapping/grinding and/or polishing operation.

Forming Semiconductor Tiles—Step 320

Semiconductor wafers are cut to form semiconductor tiles 220.Preferably, each of the tiles is provided using a scribing and breakingprocess. More preferably, scribing can be provided via a diamond stylus,laser cutting, or the like. These are preferably “standard” wafers thathave epitaxial layers grown on their front side and are ready for devicefabrication. The semiconductor tiles 220 are shaped such that thesesemiconductor tiles 220 can cover a planar surface with minimalintervening gaps. According to a specific embodiment, each of the tilesis formed along a crystalline plane, which provides an accurate shapeand form. Such accurate shape and form allows for alignment between eachof the tiles to reduce a possibility of gaps between each of the tiles.This also subsequently enables all tiles to be arranged on the metallicsubstrate with the same crystal orientation.

Bonding Tiles to Substrate—Step 330

A metallic substrate material is chosen to match the coefficient ofthermal expansion (CTE) of the chosen semiconductor over the requiredrange of processing temperatures. The substrate material is also chosenfor its strength, thermal and electrical conductivity and cost.Preferably, the substrate also has a high thermal conductivity to carryaway heat from an integrated device formed thereon. According to certainembodiments, the thermal conductivity of the metallic substrate can be165 Watts/m-Kelvin or greater.

For example, an alloy of approximately 80% molybdenum and 20% coppermatches the CTE of gallium arsenide and has suitable electrical andthermal conductivity. An advantage of using a metallic substrate 210 isthat the CTE can be adjusted by changing the composition of the metalalloy. No such adjustment is possible if a crystalline substrate such assilicon is used.

The metallic substrate 210 is polished on one face and its perimeter isshaped to suit large diameter wafer processing equipment. Preferably,polishing reduces a possibility of air gaps forming between the surfaceof the substrate and the tiles. The metallic substrate has a surfaceroughness no greater than a predetermined amount and a uniformity ofless than a certain amount across the substrate in certain embodimentsto facilitate the bonding process. According to certain embodiments, thesurface can also include a series of patterns and/or textures, whichprevent the formation of air bubbles, etc. and enhance the bondingprocess. This typically means the metallic substrate 210 is circular inshape (as represented in FIGS. 1 and 2). A minor flat on one side can beprovided, for compatibility with existing wafer processing equipment.

The metallic substrate 210 is preferably made as thin as possible so asnot to increase the weight or heat capacity of the composite structure.A typical thickness might be in the range 200 μm to 400 μm.

An inert coating layer 290 is then deposited on the metallic substrate210 if there is a risk that the substrate 210 might be effected bysubsequent semiconductor process chemistry. A thin layer (typically lessthan 1 μm in thickness) of a noble metal such as gold or platinum isgenerally suitable for this purpose. Preferably, the coating isnon-reactive with subsequent semiconductor processing steps. Othermaterials (such as silicon nitride) can also be used, provided suchmaterials have sufficient resistance to process chemistry andtemperatures used in the intended wafer processing steps.

The bonding layer 250 is deposited on the polished surface of themetallic substrate 210. This metallic bonding layer 250 is preferablymade from two or more metals that form a eutectic alloy on heating. Theoutermost layer is preferably a noble metal (such as gold) that preventsthe underlying layers from oxidising before and during bonding.Underlying layers may be formed of tin or indium. These metals arechosen such that the eutectic alloy forms at relatively low temperature(for example, 200 Degrees Celsius) and having formed, does not melt atthe elevated temperatures encountered during wafer processing. Thebonding layer may also serve as the inert coating layer for the metallicsubstrate.

A complementary bonding layer 270 is also deposited on the back-side ofeach thinned semiconductor wafer tile 220. This complementary bondinglayer 270 is also preferably metallic and its composition is chosen toprovide maximum adhesion to the semiconductor tile 220 over the range ofsubsequent processing temperatures. The preferred layer structures aretitanium/gold or titanium/platinum/gold, but many other combinations ofmetals are possible without departing from the scope and spirit of theinvention.

Numerous other bonding layer compositions are possible, and may bechosen to match particular processing requirements (such as maximumtemperature) of different semiconductor materials. For example, it maybe advantageous to form the indium or tin bonding layer on thesemiconductor wafer instead of the metal substrate in some embodiments.The advantage may come from simplifying the manufacturing processes usedto produce the metal substrate and hence reducing overall costs. In thiscase, the metal substrate's gold passivation layer also serves as thebonding layer.

The use of metallic bonding layers offers the advantage of allowingbonding to occur at relatively low temperatures (for example, 200°).This ensures the epitaxial layer structure of the wafer tiles 220 is notdegraded. Non-metallic complementary bonding layers 290 such as silicon,polysilicon, silicon dioxide or silicon nitride may also be used.

Large gaps between semiconductor tiles 220 are desirably avoided as suchgaps may adversely affect the spin-deposition of photoresist. Thesemiconductor tiles 220 are preferably square or rectangular in shape.Such shapes allow arrays of rectangular chips to be efficientlycontained inside the semiconductor tiles 220, and also allowssemiconductor tiles 220 to be cut by scribing and breaking along crystalplanes, which are typically rectangular.

However, other tile shapes may also be used. Hexagonal tiles, forexample, may cover the surface of a circular substrate 210 moreefficiently than rectangular tiles. The preferred embodiment uses a setof non-uniform square or rectangular tiles as represented in FIG. 1. Theselected pattern semiconductor tiles 220 depends on the size of theavailable semiconductor wafers, and the size of the metallic substrate210.

The semiconductor tiles 220 are positioned on top of the polishedsurface of the metallic substrate 210, such that the semiconductor tiles220 preferably abut each other (or are closely spaced together) to forma substantially continuous semiconductor surface. Small gaps (forexample, of less than 5 μm) may be advantageous for the reasons notedabove. The semiconductor tiles 220 are arranged to ensure a commoncrystal axis orientation. The semiconductor tiles 220 and metallicsubstrate 210 are then subjected to a compressive force at elevatedtemperature, which causes a eutectic alloy to form and permanently bondthe semiconductor tiles 220 to the metallic substrate 210.

In a specific embodiment, bonding occurs by placing each of the tilesoverlying the metal substrate. A bonding layer such as those describedherein as well as others is also provided. Bonding occurs usingmechanical force between each of the tiles and the substrate to compressthe bonding layer. Heating is also provided. In a specific embodiment,heating and pressure (normal to the surface of the tiles and substrate)is applied, while maintaining each of the tiles free from lateralmovement with respect to the substrate to form, for example, a eutecticbonding layer between each of the tiles and the metal substrate. Ofcourse, there can be many variations, alternatives, and modifications.

Front-Side Processing of Composite—Step 340

The front-side of the composite wafer is now processed according tostandard semiconductor fabrication techniques. Fiducial alignment marksare provided on each tile 220, to allow for slight misalignments betweensemiconductor tiles 220. Individual chips are preferably arranged on thesemiconductor tiles 220, such that the chips are wholly contained withintiles 220 and do not span semiconductor tile boundaries.

Opening Via Holes—Step 350

Unlike existing semiconductor processes, which create via holes from theback-side of a wafer toward the front-side, via holes can be made fromthe front side toward the metallic substrate 210. The alignment of viaholes is thus simplified as this alignment is relative to other visiblefront-side features.

Metallizing Via Holes—Step 360

The presence of the metallic substrate 210 allows large areas of thesemiconductor tiles 220 to be removed in the via hole process withoutcompromising the structural strength of the composite wafer. This meansthat via hole “trenches” can be formed on the semiconductor tiles 220.These trenches are able to provide the following features:

-   -   (i) relatively low inductance ground connections compared to        ordinary round vias;    -   (ii) electromagnetic screening between adjacent circuits, which        is important as circuit densities increase;    -   (iii) chip separation outlines; and    -   (iv) contouring of the semiconductor wafer to achieve localized        heat spreading features.        Cutting into Individual Devices—Step 370

The individual chips are separated by cutting the metallic substrate 210either from the front-side or back-side depending on the capabilities ofthe process machinery.

Since each chip is supported by a portion of the metallic substrate 210,chip breakage is reduced during handling. Also, larger chips may befabricated. As a result, more functions/systems may be integrated on asingle chip. Such chips offer considerable cost savings by simplifyingengineering and production requirements.

The presence of the metallic substrate 210 on each chip also serves as aheat spreader, which is advantageous in high power applications.

Further Variations

One variation of the above-described fabrication procedure is to bondun-thinned wafer tiles 220 to the metallic substrate 210. Thesemiconductor tiles 220 may be subsequently thinned when bonded to themetallic substrate 210. This variation provides the advantages of“planarising” the semiconductor surface of the wafer composite duringthe thinning process. The epitaxial device layers are, as a consequence,grown on the wafer composite.

This revised procedure may provide economic benefits in certaincircumstances. Further, handling requirements of wafer tiles 220 beforebonding are relaxed as the semiconductor tiles 220 are of greaterthickness at this stage.

A metallic bonding layer 250 is described herein, though othertechniques may be used to affix the semiconductor tiles 220 to ametallic substrate 210. For example, adhesives adapted to thetemperature and chemical processing conditions involved in semiconductorfabrication may be used to adhere semiconductor tiles 220 to a metallicsubstrate 210.

The techniques described herein are suitable for manufacturingsemiconductor devices including those using composite semiconductorslarge-diameter composite metallic substrates. As well as other benefitsdescribed herein, the described techniques potentially offer improvedradio frequency performance, improved yield and lower costs througheconomies of scale.

A method for fabricating contact regions in a semiconductor substrateaccording to an embodiment of the present invention can be outlined asfollows.

-   -   1. Provide a metallic substrate having a first diameter and        having a bonding surface;    -   2. Bond a plurality of tiles overlying the bonding surface, each        of the tiles being coupled to a portion of the bonding surface,        each of the tiles having a shape and size to be able to form an        array configuration;    -   3. Elevate a temperature of the plurality of tiles and metal        substrate;    -   4. Form a eutectic bond between each of plurality of tiles and        portion of the bonding surface, whereupon the elevating of the        temperature is provided while each of the tiles is substantially        stationary relative to the metal substrate;    -   5. Form a plurality of active devices on each of the plurality        of tiles;    -   6. Form a plurality of openings through each of tiles, each of        the openings traversing through a portion of one of the tiles        through a portion of the eutectic bond to a portion of the metal        substrate to form a via structure;    -   7. Form an interconnect layer to connect the portion of the one        of the active devices through the portion of the tile through        the eutectic bond to the portion of the metal substrate.

A method according to an alternative embodiment of the present inventioncan be outlined as follows:

-   -   1. Provide a metallic substrate having a predetermined        thickness;    -   2. Bond a first thickness of compound semiconductor material        overlying the metallic substrate;    -   3. Reduce a thickness of the first thickness of compound        semiconductor material to a second thickness;    -   4. Form one or more via structures through a portion of the        second thickness of compound semiconductor material to a portion        of the underlying metal substrate, whereupon the via structure        electrically connects to the metal substrate (using front side        processing);    -   5. Perform other steps, as desired.

The above sequence of steps provides a way of forming via structures ina multilayered substrate according to an embodiment of the presentinvention. As shown, these steps include forming a via structure throughthe compound semiconductor material onto a portion of the underlyingmetal substrate. The via structure is preferably contacted to theportion of the metal substrate. Preferably, the present invention mayovercome certain limitations of conventional methods by forming viaholes from the front side of the wafer, thereby allowing for easieralignment. By using the metallic substrate to provide mechanical supportfor the wafer, the number of via structures or density of suchstructures can increase to overcome any of the conventional restrictionson the number and shape of via holes. Depending upon the embodiment,there are many variations, alternatives, and modifications.

According to a specific embodiment, a method for fabricating a viastructure can be provided as follows.

-   -   1. A compound semiconductor structure is fabricating using one        or more processes described herein.    -   2. Photoresist is deposited, exposed and developed to cover the        front side of the wafer except where via holes are desired.    -   3. Reactive ion etching techniques are used to remove        semiconductor material down to the metallic substrate to form        openings. (The profile (slope) of the sides of these openings        can be varied by adjusting the parameters of the etching        process. The slope is adjusted to such that the diameter        decreases at the metallic substrate end of the via holes.)    -   4. Metal is deposited over the entire surface of the wafer using        evaporation, sputtering or chemical vapour deposition techniques        (The metal coats the sides of the via holes and establishes        contact between certain front side components and the ground        plane provided by the metallic substrate)    -   5. Excess metal is removed using a second photoresist layer and        appropriate etching or ion milling processes.

As shown, the via structures can be made of almost any shape and sizedepending upon the application. The method provides a way of makingelongated via openings (e.g., holes) or trenches that have very lowinductance, i.e., less than 2 pH, which provides low impedance groundconnections in high frequency (>10 GHz) circuits such as amplifiers oroscillators. The same feature can be used to provide grounded partitionson-chip, which is useful in isolating adjacent circuits that wouldotherwise interfere with each other such as radio transmitters andreceivers. Further details of the present method can be found throughoutthe present specification and more particularly below.

FIGS. 4-7 illustrate a simplified method of forming a via structureaccording to an embodiment of the present invention. This method ismerely an example, which should not unduly limit the scope of the claimsherein. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. As shown, the method beginsby providing a metallic substrate 400, which is similar to the one notedabove but can also be others. A compound semiconductor material layer401 has been bonded to the metallic substrate. Depending upon theembodiment, the compound semiconductor material 401 can be any one ofthe ones described herein, as well as others, including multilayeredstructures, depending upon the embodiment. Front side processing iscomplete except for via holes. A plurality of integrated devicestructures have been formed overlying the compound semiconductormaterial. These device structures including, among others, transistors,diodes, resistors, capacitors, inductors, and circuits made from thesecomponents such as amplifiers, mixers, switches. Of course, theparticularly integrated device structures depend upon the application.

As further shown, a photosensitive material 501 is formed overlying anupper surface of the integrated circuit device structures. Thephotosensitive material can include a photoresist, such as ShipleyMEGAPOSIT SPR 600 Series, but can also be others. The photoresistmaterial is exposed using standard front-side mask alignment techniquesand developed to form one or more patterns 503. Each of these patternsexpose an underlying region, which will be for a via structure. Theexposed region is preferably the exposed compound semiconductormaterial. As shown, the photosensitive material is provided on the frontside of the substrate, rather than the backside in a specificembodiment.

Referring to FIG. 6, the method removes the exposed portion of thecompound semiconductor material to form an opening 601, which extends tothe metal substrate. Via holes/trenches may be etched using standardetching techniques such as reactive ion etching. The opening can be ofalmost any shape and size depending upon the embodiment. The shape ispreferably elongated such as a rectangle or other like shape. The sizeis 50 microns and less or 500 microns and greater, depending upon theembodiment. Additionally, the present invention allows for more viastructures per area, i.e., via structure density. As merely an exampleusing gallium arsenide compound semiconductor material, 100 micronsthick, 25 via structures can be formed within a region of about onesquare millimeter. The method then removes the photoresist via standardstripping processes.

The method then forms metal contact structures 701 within the exposedportion of the compound semiconductor material. Metal is deposited tocover walls of via holes/trenches. The metal structure is preferablycomposed of an adhesion layer such as titanium or the like, covered by adiffusion barrier made from platinum and a contact layer made of gold orother suitable material. Other metals may be substituted in place ofthose mentioned such as substituting copper for gold. Techniques such asplating, spluttering, and/or vapor deposition are used to form the metallayer. The metal layer can also include multiple metal layers. Dependingupon the embodiment, the metal layer can be patterned to form metalinterconnect structures.

FIG. 8 is a simplified plot of a frequency characteristic of a viastructure according to an embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims herein. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. As shown, the horizontalaxis illustrates frequency while the vertical axis illustratesattenuation. The first plot illustrates a low pass filter including 16pH via structure ground connection. The second plot illustrates a 1.6 pHvia structure ground connection, which has improved stop bandattenuation. These are simple low pass filters using a single via holeto connect the filter to the ground reference. Although the inductanceof the via hole helps filter performance at one particular frequency(i.e. the frequency at which a deep notch occurs) it reduces filterperformance (attenuation) above this notch frequency. The benefit ofreducing inductance of via holes lies in increasing the attenuation ofthe filter at high frequencies. Standard via holes are round withdiameters in range 50-100 microns. They have between 8 and 16 pH ofinductance. By increasing the perimeter of the via hole (e.g. so that itforms a trench), a much lower inductance (e.g. 1 pH) can be obtained.The lower inductance is of benefit in circuits such as amplifiers andfilters which require low impedance ground connections at very highfrequencies.

A method of manufacturing bonded substrates according to an embodimentof the present invention may be outlined as follows.

-   -   1. Provide a metallic substrate;    -   2. Bond a first thickness of compound semiconductor material        overlying the metallic substrate;    -   3. Reduce a thickness of the first thickness of compound        semiconductor material to a second thickness;    -   4. Form a trench region surrounding a portion of the second        thickness of the compound semiconductor material;    -   5. Forming a conductive material within the trench region to        isolate the portion of the second thickness of the compound        semiconductor using the conductive material in the trench region        and a portion of the underlying metallic substrate; and    -   6. Perform other steps, as desired.

As shown, the method provides a way of manufacturing a bonded substrate.As merely an example, the method forms a metallic isolation structure,which encloses a portion of compound semiconductor material. Theisolated metallic structure has improved properties, e.g., greaterelectrical and thermal isolation from surrounding circuitry. Furtherdetails of the present method and resulting device can be foundthroughout the present specification and more particularly below.

FIGS. 9-15 illustrate a simplified method of forming a semiconductordevice according to an alternative embodiment of the present invention.This method is merely an example, which should not unduly limit thescope of the claims herein. One of ordinary skill in the art wouldrecognize many variations, alternatives, and modifications. As shown,the method begins by providing a metallic substrate 900, which issimilar to the one noted above but can also be others. A compoundsemiconductor material layer 901 has been bonded to the metallicsubstrate. Depending upon the embodiment, the compound semiconductormaterial 901 can be any one of the ones described herein, as well asothers, including multilayered structures, depending upon theembodiment. A plurality of integrated device structures 902 have beenformed overlying the compound semiconductor material. These devicestructures including, among others, transistors, diodes, resistors,capacitors, inductors, and circuits made from these components such asamplifiers, mixers, switches. Of course, the particularly integrateddevice structures depend upon the application.

As further shown, an insulating material 1001 is formed overlying anupper surface of the integrated circuit device structures as illustratedby FIG. 10. The insulating material can include a dielectric, such aspolyimide material, but can also be others. The polyimide material ispatterned to form one or more patterns 1001 covering only certain areasof the wafer. The polyimide is formed overlying the integrated circuitdevice and is free from attachment on other regions 1002 of the compoundsemiconductor material. Referring to FIG. 11, the method forms a metallayer 1103, which has been patterned to enclose the polyimide layer anda portion of the compound semiconductor material. Other portions of themetal have been selectively removed, as shown by reference numeral 1105.

The method patterns a region 1201 surrounding the polyimide metalsandwich layer, as shown in FIG. 12. The region is a trench region thatsurrounds the periphery of the polyimide metal sandwich layer, which isoverlying the integrated circuit device. The method can use aphotolithography and etching technique depending upon the embodiment.The trench region has a width of about 50 microns and length of about500 microns. A depth is about 50 microns but depends upon theembodiment. The method then forms a metal layer 1301 contacting themetal layer overlying the polyimide and a portion of the metal substrate901. Optionally, the polyimide layer is removed underlying the metallayer to form an “air bridge” that reduces capacitance to the integratedcircuit device or other active circuitry formed thereon. A side-viewdiagram of the device, including the air bridge, is illustrated by wayof FIG. 15. As shown, the device includes air bridge 1401 between metallayer 1103 and device structure 902. The device is provided on compoundsemiconductor layer 901, which is bonded to metal substrate 900. Viastructures are formed to connect metal substrate 1301 via metal layer1301 to metal layer 1103. As shown, the method forms a box structurearound a peripheral region of the device, which has been isolated usingthe metal box structure. Depending upon the embodiment, there can bemany variations, modifications, and alternatives. For example, althoughthe preceeding diagrams show the box “top” being formed first, the walls(i.e. trenches) could be formed first, with the top added later.

As shown, the metal layer can also act as a thermal conductive feature,which will be provided in more detail below. Here, the inventionprovides an integrated circuit device structure. The integrated circuitdevice structure includes a metallic substrate, which has apredetermined thickness and a predetermined thermal conductivity. Athickness of compound semiconductor material is bonded to a surfaceoverlying the metallic substrate. A trench region is disposed within aportion of the thickness of the compound semiconductor material andextending to a portion of the metallic substrate. A thermal conductivematerial (e.g., metal layer) is formed within the trench region andthermally coupled to the portion of the metallic substrate. The thermalconductive material is coupled (e.g., directly connected to physically)to the portion of the thickness of the compound semiconductor toredistribute thermal energy among the portion of the compoundsemiconductor, the thermal conductive material, and the metallicsubstrate. Preferably, any hot spots are prevented during operation of aresulting integrated circuit device. The metal substrate structure actsas a sink for thermal energy.

Various alterations, modifications and substitutions can be made to thearrangements and techniques described herein, as would be apparent toone skilled in the relevant art in the light of this disclosure withoutdeparting form the scope and spirit of this invention.

1. A method for manufacturing composite substrates for semiconductordevices, the method comprising: providing a metal substrate, the metalsubstrate having a first diameter and having a bonding surface; bondinga plurality of tiles overlying the bonding surface, each of the tilesbeing coupled to a portion of the bonding surface, each of the tileshaving a shape and size to be able to form an array configuration;elevating a temperature of the plurality of tiles and metal substrate;forming a eutectic bond between each of plurality of tiles and portionof the bonding surface, whereupon the elevating of the temperature isprovided while each of the tiles is substantially stationary relative tothe metal substrate; forming a plurality of active devices on each ofthe plurality of tiles; forming a plurality of openings through each oftiles, each of the openings traversing through a portion of one of thetiles through a portion of the eutectic bond to a portion of the metalsubstrate to form a via structure; forming an interconnect layer toconnect the portion of the one of the active devices through the portionof the tile through the eutectic bond to the portion of the metalsubstrate; whereupon the interconnect layer that connects the portion ofone of the active devices through the portion of one of the tilesthrough the portion of the eutectic bond to the portion of the metalsubstrate.
 2. The method of claim 1 wherein the forming of the pluralityof openings in each of the tiles further comprises coating the pluralityof active devices using a photolithographic material and patterning thecoating to form regions corresponding to the openings.
 3. The method ofclaim 2 wherein the patterning comprises an etching process.
 4. Themethod of claim 1 wherein each of the tiles comprises an entity selectedfrom gallium arsenide, indium phosphide, gallium nitride, and siliconcarbide.
 5. The method of claim 1 wherein each of the openings is a viastructure.
 6. The method of claim 1 wherein the eutectic bond isprovided using an alloy selected from a low melting temperature metalincluding indium, tin and an oxidation-resistant metal.
 7. The method ofclaim 1 wherein the array configuration is an N by M array of the tiles,each of the tiles being coupled to another tile.
 8. The method of claim1 wherein each of the openings is characterized by an aspect ratio ofgreater than 2 to
 1. 9. The method of claim 1 wherein the interconnectlayer comprises gold over platinum over titanium.
 10. The method ofclaim 1 wherein the interconnect layer comprises a barrier metal layerunderlying a conductive layer.
 11. The method of claim 1 wherein themetal substrate provides a ground plane.
 12. A method of manufacturingbonded substrates, the method comprising: providing a metallicsubstrate, the metal substrate having a predetermined thickness; bondinga first thickness of compound semiconductor material overlying themetallic substrate; reducing a thickness of the first thickness ofcompound semiconductor material to a second thickness; and forming oneor more via structures through a portion of the second thickness ofcompound semiconductor material to a portion of the underlying metalsubstrate, whereupon the via structure electrically connects to themetal substrate.
 13. The method of claim 12 wherein the second thicknessof compound semiconductor substrate is less than 100 microns.
 14. Themethod of claim 13 wherein the second thickness of compoundsemiconductor material is unstable without the metal substrate.
 15. Themethod of claim 13 wherein the via structure has an aspect ratio isgreater than 2 to
 1. 16. The method of claim 12 wherein the metalsubstrate is characterized by a first thermal expansion coefficient andthe compound semiconductor is characterized by a second thermalexpansion coefficient, whereupon the first thermal expansion coefficientis within a predetermined amount of the second thermal expansioncoefficient.
 17. The method of claim 12 wherein the predetermined amountis characterized to prevent any damage to the compound semiconductorthrough a temperature range from about room temperature to 550 DegreesCelsius.
 18. The method of claim 12 further comprising processing thesecond thickness of compound semiconductor through one or moremanufacturing processes for integrated circuits.
 19. The method of claim18 wherein the one or more manufacturing processes includes at least analloying process to form a contact between the compound semiconductorand a metal layer.
 20. The method of claim 19 wherein alloying processis an annealing process.
 21. A method of manufacturing bondedsubstrates, the method comprising: providing a metallic substrate, themetallic substrate having a predetermined thickness; bonding a firstthickness of compound semiconductor material overlying the metallicsubstrate; reducing a thickness of the first thickness of compoundsemiconductor material to a second thickness; and forming one or moretrench structures through a portion of the second thickness of thecompound semiconductor through a side opposite of a backside of themetallic substrate; forming one or more metal structures within the oneor more trench structures to form one or more respective via structureswithin the portion of the second thickness of compound semiconductormaterial to a portion of the underlying metal substrate, whereupon thevia structure electrically connects to the metal substrate.
 22. A methodof manufacturing bonded substrates, the method comprising: providing ametallic substrate, the metal substrate having a predeterminedthickness; bonding a first thickness of compound semiconductor materialoverlying the metallic substrate; reducing a thickness of the firstthickness of compound semiconductor material to a second thickness; andforming a trench region surrounding a portion of the second thickness ofthe compound semiconductor material; and forming a conductive materialwithin the trench region to isolate the portion of the second thicknessof the compound semiconductor using the conductive material in thetrench region and a portion of the underlying metallic substrate. 23.The method of claim 22 exposing an upper portion of the portion of thesecond thickness of the compound semiconductor.
 24. The method of claim22 further comprising forming an insulating layer overlying the exposedupper portion.
 25. The method of claim 24 further comprising forming ametal layer overlying the insulating layer and connecting to theconductive material in the trench region to enclose the portion of thesecond thickness of the compound semiconductor.
 26. A substratestructure for high frequency devices, the structure comprising: ametallic substrate, the metallic substrate being a ground plane for ahigh frequency amplifying device operable at a frequency greater than 10G Hz; a compound semiconductor material bonded to the metallicsubstrate; one or more via structures for ground connections formedwithin portions of the compound semiconductor material, the one or morevia structures being electrically connected to the metallic substrate;whereupon the one or more via structures are configured to provide adesired reactance to provide a universal ground reference, the universalground reference is within a predetermined amount.
 27. The structure ofclaim 26 wherein predetermined amount is less than one quarter of thewavelength of the operating frequency of the circuit.
 28. The structureof claim 26 wherein the desired reactance ranges from about 0.01 ohm toabout 1 ohm.
 29. An integrated circuit device structure, the integratedcircuit device structure comprising: a metallic substrate, the metalsubstrate having a predetermined thickness and a predetermined thermalconductivity; a thickness of compound semiconductor material bonded to asurface overlying the metallic substrate; and a trench region disposedwithin a portion of the thickness of the compound semiconductor materialand extending to a portion of the metallic substrate; and a thermalconductive material formed within the trench region and thermallycoupled to the portion of the metallic substrate, the thermal conductivematerial being coupled to the portion of the thickness of the compoundsemiconductor to redistribute thermal energy among the portion of thecompound semiconductor, the thermal conductive material, and themetallic substrate.
 30. The structure of claim 29 wherein the trenchregion surrounds the portion of the thickness of the compoundsemiconductor material.
 31. The structure of claim 29 wherein thesubstrate is a heat sink.
 32. The structure of claim 29 wherein theredistributed thermal energy provides the portion of the compoundsemiconductor free from one or more hot spots.